Quantum-dot Cellular Automata (QCA) technology has been extensively conceivable as an alternative to Complementary Metal Oxide Semiconductor (CMOS) due to faster speed, smaller size, lower power consumption, higher scale integration and higher switching frequency. This paper present a novel design of Fredkin Gate (FG) based on QCA logic gates: the QCA wire, Majority gate and Inverter gate. Furthermore, compared to a previous design, the number of cells, covered area, and time delay of the proposed Fredkin Gate (FG) are reduced by 62.20%, 76.70%, and 25%, respectively and also obviate coplanar wire-crossing. Here, QCADesigner a common QCA layout design and verification tool is employed to verify and simulate the proposed Fredkin Gate (FG). The proposed circuit is a promising constructing in low power consuming fault-tolerance system and can stimulate higher degree of integrated applications in QCA.