In the current scenario, with the increasing integration densities, most system-on-chip designs are migrating towards asynchronous logic .In this paper a novel asynchronous SRAM design, operating without a global clock signal is proposed. The results obtained from proposed design are in perfect accordance with theoretical expectations. The comparison with the conventional synchronous version reveals that the proposed design is faster and is more power efficient. Timing and Power Analysis of the proposed and conventional SRAM blocks are carried out to show the improvement achieved through the proposed model. For Power analysis models are simulated using xPower analyser tool which is bundled with Xilinx ISE v9.2.For Timing analysis the designs presented in this paper were implemented in TSMC 90 nm CMOS technology and simulated at 2.5V using PSpice. The proposed asynchronous SRAM design outperforms the existing design in terms of accuracy, power and speed.