In this paper, a low-power high-efficient Hybrid LDPC Decoder Architecture for high error detection and correction applications is proposed. The majority logic circuit is integrated with LDPC decoder in order to reduce the maximum number of errors. The existing architecture requires a large decoding time. For memory applications, this increases the memory access time. The proposed hybrid method detects for errors in a word in the first iteration of majority logic decoding. If no errors are detected, then the decoding stops and remaining iterations are not performed. The scope of this paper is to reduce the decoding latency and hardware complexity by ending the decoding process if errors are not detected. The architecture is synthesized on Xilinx 9.2i and targeted to 90nm device. Synthesis report shows that the proposed architecture reduces the decoding latency and power consumption when compared to the conventional architecture design.