Modern DSP systems are often well suited to VLSI implementation. Indeed, they are economically viable only if implemented using VLSI technologies. It has significant industrial and commercial relevance. Many DSP systems are produced in very large numbers and require high performance. It is easy to implement FIR filters but has more hardware complexity due to the use of multipliers in the circuit. In this paper, the design of a multiplierless fixed point FIR filter is presented. By restricting the multipliers, achieve a low power and less area requirements. The response of the filter is also accurate. An efficient multiplierless fixed point FIR filter can be designed by Shift Add architecture. Further the area and power reduced by using the Common Subexpression Elimination (CSE) and Level Constrained Common Subexpression Elimination (LCCSE) methods. In this architecture, existing all multipliers replaced by a single block in which shifting and adding operations are performed. In this paper deals, by using navel shift-add architecture, hardware complexity and power consumption is reduced.